1. Field of the Invention
The present invention relates to a semiconductor structure, a method for improving its ESD strength and a method for improving its overload strength.
2. Description of the Prior Art
The present invention in particular relates to ESD endangered semiconductor devices (ESD=Electro Static Discharge). Such ESD endangered devices are in particular devices whose parasitic capacities are considerably smaller than the source capacities in an ESD test process. With the so-called human body model (HBM) the capacities lie in the range of about 100 pF. Among the relevant devices are high frequency diodes and high frequency bipolar transistors. With bipolar transistors either the emitter-base or the base-collector distance represents the weak point with regard to an ESD load depending on technology.
The present invention further particularly relates to semiconductor devices endangered by destruction through occurring overvoltages, wherein such overvoltage endangered devices, like also in the ESD case, e.g. include high frequency diodes and high frequency bipolar transistors. With a voltage or a current overload, e. g. caused by transitions or a faulty RF-adaption, the emitter-base distance or the base-emitter distance is mainly endangered, like in the ESD-case. They may break through, and an avalanche-like rising current may cause an irreversible damage of the device.
With the electronic devices, as they are manufactured and used today with always decreasing geometries with a simultaneous increase of integration density, there is a danger of damaging or destroying them due to the rising sensitivity in the case of electrostatic discharges. The devices have therefore to be protected against such electrostatic discharges, which can on the one hand be obtained by handling them accordingly in chip zones, which however only prevents the entering of the electrostatic discharge without the devices themselves comprising any protective measures.
Critical devices are frequently supported by external, additional components. In integrated circuits mainly diodes (“protection diode”) in different versions are used herefore, often as a double diode in a “back to back” arrangement. Such a protective diode is e. g. connected against mass in parallel to the very sensitive gate contact of an MOS transistor. In case of an overvoltage it breaks through and therefore leads off the dangerous ESD charge to the mass.
With applications in the area of microns such protective elements are unwanted, however, as they massively affect the high frequency properties due to their parasitic capacities also in the reversing case. Apart from that, such external protective measures only operate restrictedly; in any case it is sensible to optimize the active device to an optimum ESD strength.
Apart from these “passive” protective measures approaches exist in the art aiming to distribute the current as far as possible when entering an ESD case. For this reason it is tried to reach a planar instead of a locally restricted breakthrough. To this end the design of the semiconductor device is rounded, as spherical dopant profiles occur in the corners which break through first. If cylindrical areas along the edges do not change into the breakthrough fast enough, this can lead to a thermal destruction of a semiconductor device. The disadvantage of these proceedings is, however, that the optimization is restricted to only surface-near parts of the semiconductor device.
In the following, the results of an ESD case are described in more detail using an exemplary semiconductor structure. In FIG. 1A a semiconductor structure is shown having a high-doped substrate 100, on which a first layer 102, e. g. an epitaxy layer has grown. As an example it is assumed that an additional layer 104 has grown on the epitaxy layer 102. The layers 102 and 104 are low-doped. The layers 102 and 104 are of the n-type, whereas the layer 104 is of the p-type, so that a pn-transition is formed at the interface between the first layer 102 and the second layer 104, which is poled in the reverse direction in FIG. 1A, as is schematically illustrated by the polarity applied to the terminals 106 and 108. In FIG. 1A the space charge region is also illustrated, which is formed around the pn-transition. In FIG. 1A a state is shown, in which no ESD case is present.
If an ESD case occurs, the current intensity is low in case of a breakthrough, however passes through a steep characteristic curve predetermined by the model in the test in the further ESD event, so that soon after the occurrence of a breakthrough high-current effects become important. In the ESD test according to the human body model the current lies within the range of amperes after a few nanoseconds. As the charge carriers produced by the avalanche effect in the space charge region have to carry current at any time of the HBM pulse, as many charge carriers are produced, so that the space charge region is shifted to the next high-doped area. This is e. g. described in more detail by Yuan Taur et al in “Fundamentals of Modern VLSI Devices”, Cambridge University Press, 1998, pp. 320 to 325, and by Betrand G. et al in “Analysis and Compact Modeling of a Vertical Grounded-Base NPN Bipolar Transistor used as an ESD Protection in a Smart Power Technology”, IEEE BCTM 1, 2, 2000, pp. 28 to 31.
In FIG. 1B, showing the semiconductor structure from FIG. 1A in the ESD case, this state is illustrated. In FIG. 1B an extended p-area is shown at 110, and as it can be seen, the space charge region is shifted to the transition border from the first layer 102 to the substrate 100.
The above-described effect of the breakthrough leads to the electrical field consequently concentrating on the area between the epitaxy layer 102 and the high-doped substrate 100. At this point the highest fields occur in the further process of the ESD result, so that here the actual ESD event takes place.
Regarding the above-mentioned implementations the disadvantages of the above-described approaches for distributing current in the ESD case become obvious, as it can be seen that the ESD strength can hardly be influenced by technological measures at the surface.
Similar effects as those encountered above using the ESD event with semiconductor structures are also encountered with semiconductor structures which are for example arranged in a power output stage and exposed to overvoltages or current impulses, which may for example result due to transitions on a supply line or due to a faulty adaption of the semiconductor structure.
JP 20000-058870 A describes a semiconductor device of improved ESD strength, wherein the device comprises an n+ substrate, whereon an n− layer is formed, in which an p+ well is inserted. US 6,232,822 B1 describes a semiconductor device, particularly a bipolar transistor, wherein a buried n+ layer is formed on a p substrate, whereon again an n collector layer is disposed, wherein a base layer is inserted. An emitter layer is formed in the base layer. Starting from a doping in the n collector layer, the n doping gradually rises to the n+ doping in the buried layer.
It is the object of the invention to provide a semiconductor structure having an improved ESD and overload strength as well as a method for improving the ESD strength and the overload strength of a semiconductor structure.
In accordance with a first aspect the present invention provides a semiconductor structure having a base layer of a first conductivity type; a first layer of the first conductivity type arranged on the base layer and having a dopant concentration which is lower than a dopant concentration of the base layer; and a second layer of a second conductivity type being operative with the first layer in order to form a junction between the first conductivity type and the second conductivity type; wherein a course of a dopant profile is set step-shaped at the transition between the base layer and the first layer starting from a first dopant concentration in the first layer via a second dopant concentration in the base layer to a third dopant concentration in the base layer, wherein the third dopant concentration is higher than the first dopant concentration and the second dopant concentration, and wherein the second dopant concentration is higher than the first dopant concentration.
In accordance with a second aspect the present invention provides a method for improving the ESD strength and the overload strength of a semiconductor structure, wherein the semiconductor structure comprises a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration which is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type, wherein the first layer and the second layer are operative in order to form a junction between the first conductivity type and the second conductivity type, wherein step-shaped setting a course of the dopant profile at the transition between the base layer and the first layer, starting from a first dopant concentration in the first layer via a second dopant concentration in the base layer to a third dopant concentration in the base layer, wherein the third dopant concentration is higher than the first dopant concentration and the second dopant concentration, and wherein the second dopant concentration is higher than the first dopant concentration.
The present invention provides a method for improving the ESD strength of a semiconductor structure, wherein the semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration which is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type, wherein the first layer and the second layer function together to form a transition between the first conductivity type and the second conductivity type, wherein the method includes the step of setting a course of the dopant profile at the transition between the base layer and the first layer, such, that with in ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.
The base layer is a substrate according to one embodiment and a buried layer according to a further embodiment.
The present invention further provides a method for improving the overload strength of a semiconductor structure, wherein the semiconductor structure comprises a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration lower than a dopant concentration of the base layer, and a second layer of a second conductivity type, wherein the first layer and the second layer are operative in order to form a transition between the first conductivity type and the second conductivity type, wherein the method includes the following step:
step-shaped setting of the doping profile at the transition between the base layer and the first layer.
According to one embodiment, the base layer includes a substrate layer and a buffer layer. Preferably the first layer is doped lower than the buffer layer. The first layer is used as an active area of the semiconductor structure. The buffer layer is only loaded with high field strengths in the overload case. In a preferred embodiment, the doping profile proceeds from about 1016 atoms/cm3 in the area of the first layer over about 1017 atoms/cm3 to about 1018 atoms/cm3 in the buffer layer to about 1019 atoms/cm3 in the area of the substrate layer.
In one embodiment an active collector of a transistor is formed in the first layer, and a base and an emitter of the transistor are formed in the second layer, wherein the transistor may be a power transistor. The transistor may be a bipolar transistor or a field effect transistor. Alternatively, a diode may be formed in the first layer and in the second layer.
The present invention is based on the findings that a distribution of current by measures at the surface of a semiconductor device influences its ESD strength only marginally, as in the ESD case the breakthrough anyway is shifted to the transition of epitaxy layer/substrate and/or epitaxy layer/buried layer—and thus being shifted in the plane. Regarding the above mentioned terminology it is noted that with bipolar transistors produced using IC technologies (IC=integrated circuit) the substrate corresponds to the “buried layer”. For simplicity in the course of the following description of the present invention reference is always made to the substrate, wherein the principles of the present invention may also be applicable for IC devices.
Instead of the measures restricted to the surface of the semiconductor structure which only result in a marginal affection of the ESD strength, as was mentioned above, the present invention teaches that an intervention is necessary only in the depth of the semiconductor device, at the transition from the epitaxy layer to the substrate.
As the steepness of a dopant profile at the transition determines the electrical fields occurring there, also the ESD strength is considerably influenced hereby, as far as no other technological shortcomings are present. The slower the dopant profile rises to the substrate, the further the space charge region must reach into the substrate, so that with a constant reverse voltage and/or a constant current a low maximum electrical field is applied and therefore an increased ESD strength is achieved.
According to the present invention between ESD strengths at the pn-transition of between 300 V and 3900 V may be obtained depending on the flatness of the profile at the transition, as it is e. g. formed along the base-collector distance of a high frequency bipolar transistor.
According to a first embodiment of the present invention the effect of a flat dopant profile is reached by subjecting the transition between the epitaxy layer and the substrate to a heat treatment after the growing of the epitaxy layer and if applicable after the formation of further structures, so that the dopant profile is flattened at the transition. With an alternative embodiment the flattening of the profile is reached without a thermal treatment only by an overall implantation into the substrate.
In a further preferred embodiment, the effect of a flat transition is reached by a step-shaped course of the dopant profile.
In the prior art almost nothing was published referring to the topic substrate/ESD strength, wherein in this context reference is made to the publication of Amerasekera A. et al., “ESD in Silicon Integrated Circuits”, John Wiley & Sons, 1995, pp. 186 to 188. The great influence of the dopant profile on the ESD strength at the transition from the epitaxy layer to the substrate was not yet detected. It is described, however, that in the ESD case the field is shifted in the direction of the substrate, it was not detected, however, that this area is therefore relevant for ESD-improving interventions. In particular no technological measures are known that could be derived from this detection for increasing the ESD strength. No concrete proposals regarding an ESD-optimized transition from the epitaxy layer to the substrate are known.
According to the present invention it is taught in deviation from the approaches known in the art, to flatten the dopant profile at the transition from the epitaxy layer to the substrate in order to increase the ESD strength.
Experiments carried out in connection with the present invention have shown, that the relatively bad ESD strength of modern technologies may not only be attributed to the results of the capacities steadily becoming smaller with miniaturization, as is often explained, but mainly to the result of the low temperature budget used in the production of semiconductors structures, which leads to steep profiles at the transition from the epitaxy layer to the substrate.
According to the present invention, the profile of the transition from the epitaxy layer to the substrate is flatter than it would be the case with conventional temperature budgets, which are used for the remaining surface-near transitions of the device. According to an embodiment of the present invention, one or more temperatures are used even for the purpose of flattening the dopant profile at the transition form the epitaxy layer to the substrate.
According to a further aspect, the present invention provides a semiconductor structure, wherein the base layer includes a substrate layer and a buffer layer, wherein the doping profile proceeds from about 1016 atoms/cm3 in the area of the first layer over about 1017 atoms/cm3 to about 1018 atoms/cm3 in the buffer layer to about 1019 atoms/cm3 in the area of the substrate layer. In one embodiment an active collector of a transistor is formed in the first layer, and in the second layer a base and an emitter of the transistor are formed, wherein the transistor may be a power transistor. The transistor may be a bipolar transistor or a field effect transistor. Alternatively, a diode is formed in the first layer and in the second layer.
The above described aspect is based on the findings, that the approaches taught above in combination with the ESD case are useable also with power devices for improving the ESD strength of transistors by providing a step-shaped dopant profile, wherein similar effects as in the ESD case occur due to occurring overvoltages at the output of such semiconductor structures.